MIPS Technologies' Publishes EEMBC Benchmarks for Industry Standard MIPS64 20Kc Core

MOUNTAIN VIEW & EL DORADO HILLS, Calif.--(BUSINESS WIRE)--Jan. 22, 2003--

Highest-performance licensable core running at 600Mhz

performance tested on the five application-based benchmark suites

MIPS Technologies, Inc. (Nasdaq:MIPS)(Nasdaq:MIPSB), a leading provider of industry-standard processor architectures and cores for digital consumer and business applications, today published their certified Embedded Microprocessor Benchmark Consortium (EEMBC) benchmark scores for the MIPS64(TM) 20Kc(TM) core, running at 600Mhz against all five of EEMBC's application-based benchmark suites.

EEMBC, a non-profit organization, works collaboratively with member companies such as MIPS Technologies to develop performance benchmarks for key embedded applications--telecommunications, consumer, networking, office automation, and automotive/industrial. EEMBC's benchmarks are based on the fundamental algorithms and functions of these applications and represent workloads that provide good metrics for comparing system performance.

The MIPS64 20Kc test chip running at a core operating frequency of 600MHz and using a compiler from Green Hills Software, received the following consolidated scores in out-of-the-box (Version 1.1) benchmark tests:

        ---------------------------- --------------------------
        Telemarks                    10.20
        ---------------------------- --------------------------
        Consumermarks                39.42
        ---------------------------- --------------------------
        Netmarks                     10.62
        ---------------------------- --------------------------
        OAmarks                      519.87
        ---------------------------- --------------------------
        Automarks                    401.34
        ---------------------------- --------------------------

"We are delighted with the publication of the 20Kc scores for the MIPS architecture, one of the most widely adopted and broadly used architectures available. By publishing their certified benchmark scores, MIPS has provided engineers an objective means of evaluating their technology and validated the system-level performance achievable with the 20Kc core," said Markus Levy, EEMBC president. "EEMBC provides out-of-the-box performance analysis for standard products like the 20Kc. Other licensees of the MIPS architecture who have published their EEMBC scores include IDT, Intrinsity, NEC, and Toshiba."

The 20Kc core is the fastest licensable embedded microprocessor IP available, with a typical operating frequency of 600MHz and a worst case operating frequency of 533MHz at TSMC's 0.13um process technology node. It's availability as a full custom hardened processor core from multiple foundries enables semiconductor companies to quickly get to market with an advanced high performance SOC design, while working with their choice of available foundry processes.

The 20Kc is an implementation of the MIPS64 instruction set architecture and a full dual issue superscalar machine implementing a 7-stage pipeline. It includes an IEEE754 compliant SIMD Floating-Point-Unit (FPU) with MIPS-3D(TM) graphics extensions. The 20Kc core can execute 2 integer instructions or 1 integer and 1 floating point instruction per cycle. At an operating frequency of 600MHz, the core delivers 1020 DMIPS of integer performance (Version 2.1, no inlining), 2.4 GFLOPS peak floating point performance, and 30M Polygons/sec of geometry processing performance.

This core is an ideal processor solution for high performance applications in digital consumer and networking segments such as laser printers in office automation, high-speed line cards, routers and cellular base-stations in networking, network storage devices and high-end digital consumer devices including integrated Telematics systems for vehicles and digital televisions.

"The results of our EEMBC benchmarks confirm that the 20Kc core is ideally suited for applications that demand exceptional performance. When combined with our SOC-it system controller, the challenges faced by high-end SOC designers are greatly simplified," said Brad Holtzinger, director of system solutions at MIPS Technologies.

For additional information regarding the certification process and guidelines for interpreting these scores, please see the backgrounder entitled, "Interpreting EEMBC Benchmark Scores of the MIPS64(TM) 20Kc(TM) Core," also published today.

Detailed score reports on the MIPS64 20Kc core are available for free from the 'Search Benchmark Scores' area of the EEMBC web site (www.eembc.org) or direct from the following URLs:

Telecommunications

Consumer

Networking

Office automation

Automotive/industrial

About EEMBC

EEMBC, the Embedded Microprocessor Benchmark Consortium was formed in 1997 to develop meaningful performance benchmarks for processors and compilers in embedded applications. Through the combined efforts of its members--more than 55 of the world's leading semiconductor, intellectual property, compiler, and RTOS companies--EEMBC(R) benchmarks have become an industry standard for evaluating the capabilities of embedded processors and compilers according to objective, clearly-defined, application-based criteria.

About MIPS Technologies

MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of compatible, robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.

MIPS is a registered trademark in the United States and other countries, and MIPS64, 20Kc and MIPS-3D are trademarks of MIPS Technologies, Inc. EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium. All other trademarks referred to herein are the property of their respective owners.

CONTACT: MIPS Technologies, Inc.          
             Lee Garvin Flanagin, 650/567-5180                 
             flanagin@mips.com                
             or
             Wall Street Communications (For EEMBC)
             Bob Decker, 415/409-0233               
             bob.decker@wallstcom.com